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1 of 16 general description the ds1338 serial real - time clock (rtc) is a low - power, full binary - coded decimal (bcd) clock/calendar plus 56 bytes of nv sram. address and data are transferred serially through an i 2 c interface. the clock/calendar provides seconds, minutes, hours, day, date, month, and year information. the end of the month date is automatically adjusted for months with fewer than 31 days, including corrections for leap year. the clock operates in either the 24 - hour or 12 - hour fo rmat with am/pm indicator. the ds1338 has a built - in power - sense circuit that detects power failures and automatically switches to the backup supply, maintaining time and date operation applications handhelds (gps, pos terminal) consumer electronics (set - top box, digital recording, network appliance) office equipment (fax/printer, copier) medical (glucometer, medicine dispenser) telecommunications (router, switcher, server) other (utility meter, vending machine, thermostat, modem) ul is a registered trademark of underwriters laboratories inc. typical operating circuit benefits and features ? completely manages all timekeeping functions o rtc counts seconds, minutes, hours, date of the month, month, day of the week, and year with leap - year compe nsation valid up to 2100 o 56 - byte, battery - backed, general - purpose ram with unlimited writes o programmable square - wave output signal ? surface - mount package with an integrated crystal (ds1338c) saves additional space and simplifies design ? interf aces with most microcontrollers o i 2 c serial interface ? low - power operation extends ba ttery backup run time o automatic power - fail detect and switch circuitry ? - 40 c to +85 c industrial temperature range supports o perati on in a wide range of applications ? underwriters laborator ies (ul ? ) recognized ordering information par t temp range pin - package top mark ? DS1338Z - 18+ - 40c to +85c 8 so (0.150 ) ds1338 - 18 DS1338Z - 3+ - 40c to +85c 8 so (0.150 ) ds1338 -3 DS1338Z - 33+ - 40c to +85c 8 so (0.150 ) ds133833 ds1338u - 18+ - 40c to +85c 8 sop 1338 rr - 18 ds1338u - 3+ - 40c to + 85c 8 sop 1338 rr -3 ds1338u - 33+ - 40c to +85c 8 sop 1338 rr - 33 ds1338c - 18# - 40c to +85c 16 so (0.300 ) ds1338c - 18 ds1338c - 3# - 40c to +85c 16 so (0.300 ) ds1338c -3 ds1338c - 33# - 40c to +85c 16 so (0.300 ) ds1338c - 33 rr = second line, revision level + denotes a lead (pb) - free/rohs - compliant device. # denotes a rohs - compliant device that may include lead that is exempt under the rohs requirements. the lead finish is jesd97 category e3, and is compatible with both lead - based and lead - free soldering processes. ? a + anywhere on the top mark denotes a lead - free device. a # denotes a rohs - compliant device. pin configurations appear at end of data sheet. ds1338 cpu v cc v cc v cc sda scl gnd x2 x1 v cc r pu r pu crystal sqw/out v bat i r pu = t r /c b ds1338 i 2 c rtc with 56 - byte nv ram 19 - 6019; rev 4 /1 5 downloaded from: http:///
2 of 16 absolute maximum ratings voltage range on any pin relative to ground.... - 0.3v to +6.0v operating temperature range ..- 40c to +85c storage temperature range... - 55c to +125c lead temperature (soldering, 10s) . . +260c soldering temperature (reflow) . +260c stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. these ar e stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated i n the operational sections of the specifications is not implied. exposure to the absolute maximum rating conditions for extended periods may affec t device reliability. recommended dc operating conditions (v cc = v cc(min) to v cc(max) , t a = - 40c to +85c, unless otherwise noted. typical values are at t a = +25c, unless otherwise noted.) (note 1) parameter symbol conditions min typ max units supply voltage v cc ds1338 - 18 1.71 1.8 5.5 v ds1338 -3 2.7 3.0 5.5 ds1338 - 33 3.0 3.3 5.5 logic 1 v ih (note 2) 0.7 x v cc v cc + 0.3 v logic 0 v il (note 2) - 0.3 +0.3 x v cc v power - fail voltage v pf ds1338 - 18 1.51 1.62 1.71 v ds1338 -3 2.45 2.59 2.70 ds1338 - 33 2.70 2.82 2.97 v bat input voltage v bat (note 2) 1.3 3.0 3.7 v dc electrical characteristics (v cc = v cc(min) to v cc(max) , t a = - 40c to +85c, unless otherwise noted. typical values are at v cc = typ , t a = +25c, unless otherwise noted.) (note 1) parameter symbol conditions min typ max units input leakage i li (note 3) 1 a i/o leakage i lo (note 4) 1 a sda logic 0 output i olsda v cc > 2v; v ol = 0.4v 3.0 ma v cc < 2v; v ol = 0.2 x v cc 3.0 sqw/out logic 0 output i olsqw v cc > 2v; v ol = 0.4v 3.0 ma 1.71v < v cc < 2v; v ol = 0.2 x v cc 3.0 1.3v < v cc < 1.71v; v ol = 0.2 x v cc 250 a active s upply current (note 5) i cca ds1338 - 18 : v cc = 1.89v 75 150 a ds1338 -3 : v cc = 3.30v 110 200 ds1338 - 33 v cc = 3.63v 120 200 v cc = 5.5v 325 standby current (note 6) i ccs ds1338 - 18 : v cc = 1.89v 60 100 a ds1338 -3 : v cc = 3 .30v 80 125 ds1338 - 33 v cc = 3.63v 85 125 v cc = 5.5v 200 v bat leakage current (v cc active) i batlkg 25 100 na downloaded from: http:///
ds133 8 3 of 16 dc electrical characteristics ( v cc = 0v, t a = - 40c to +85c , unless otherwise noted. typical values are at v bat = 3.0v, t a = +25 c, unless otherwise noted. ) ( note 1) parameter symbol min typ max units v bat current (osc on); v bat = 3.7v, sqw/ out off (note 7) i batosc1 800 1200 na v bat current (osc on); v bat = 3.7v, sqw/ out on (32khz) (note 7) i batosc2 1025 1400 na v bat data - ret ention current (osc off); v bat = 3.7v (note 7) i batdat 10 100 na ac electrical characteristics (v cc = v cc(min) to v cc(max) , t a = - 40c to +85c) (note 1) parameter symbol condition min typ max units scl clock frequency f scl fast mode 100 400 khz s tandard mode 0 100 bus free time between stop and start condition t buf fast mode 1.3 s standard mode 4.7 hold time (repeated) start condition (note 8) t hd:sta fast mode 0.6 s standard mode 4.0 low period of scl clock t low fast mode 1.3 s standard mode 4.7 high period of scl clock t high fast mode 0.6 s standard mode 4.0 setup time for repeated start condition t su:sta fast mode 0.6 s standard mode 4.7 data hold time (notes 9, 10) t hd:dat fast mode 0 0.9 s standard mode 0 data setup time (note 11) t su:dat fast mode 100 ns standard mode 250 rise time of both sda and scl signals (note 12) t r fast mode 20 + 0.1c b 300 ns standard mode 20 + 0.1c b 1000 fall time of both sda and scl signals (note 12) t f fast mode 20 + 0.1c b 300 ns standard mode 20 + 0.1c b 300 setup time for stop condition t su:sto fast mode 0.6 s standard mode 4.0 capacitive load for each bus line c b (note 12) 400 pf i/o capacitance (sda, scl) c i/o (note 13) 10 pf oscillator stop flag (osf) delay t osf (note 14) 100 ms downloaded from: http:///
ds133 8 4 of 16 power-up/power- down characteristics (t a = - 40c to +85c) (note 1, figure 1) parameter symbol min typ max units recovery at power - up (note 15) t rec 2 ms v cc fall time; v pf(max) t o v pf(min) t vccf 300 s v cc rise time; v pf(min) to v pf(max) t vccr 0 s warning: negative undershoots below - 0.3v while the part is in battery - backed mode may cause loss of data. note 1: limits at - 40c are guaranteed by design and not production te sted. note 2: all voltages are referenced to ground. note 3: scl only. note 4: sda and sqw/ out. note 5: i cca scl clocking at max frequency = 400khz. note 6: specified with the i 2 c bus inactive. note 7: measured with a 32.768khz crystal attached to x1 and x2. note 8: after this period, the first clock pulse is generated. note 9: a device must internally provide a hold time of at least 300ns for the sda signal (refer red to the v ih(min) of the scl signal) to bridge the undefined region of the falling e dge of scl. note 10: the maximum t hd:dat need only be met if the device does not stretch the low period (t low ) of the scl signal. note 11: a fast - mode device can be used in a standard - mode system, but the requirement t su:dat to 250ns must then be met. this is automatically the case if the device does not stretch the low period of the scl signal. if such a device does stretch the low period of the scl signal, it must output the next data bit to the sda line t r(max) + t su:dat = 1000 + 250 = 1250ns before the scl line is released. note 12: c b total capacitance of one bus line in pf. note 13: guaranteed by design. not production tested. note 14: the parameter t osf is the time period the oscillator must be stopped for the osf flag to be set over the voltage range of 0.0v v cc v cc(max) and 1.3v v bat 3.7v. note 15: this delay applies only if the oscillator is enabled and running. if the oscillator is disabled or stopped, n o power - up delay occurs. figure 1 . power - up/power - down timing outputs v cc v pf(max) v pf(min) inputs high -z don't care valid recognized recognized valid t vccf t vccr t rec downloaded from: http:///
ds133 8 5 of 16 figure 2 . timing diagram figure 3 . block diagram ram (56 x 8) serial bus interface and address register control logic 1hz 1hz/4.096khz/8.192khz/32.768khz mux/ buffer user buffer (7 bytes) clock, calendar, and control registers "c" version only power control ds1338 x1 c l c l x2 sda scl sqw/out v cc gnd v bat oscillator and divider n downloaded from: http:///
ds133 8 6 of 16 typical operating characteristics i bat vs. v bat 550 600 650 700 750 800 850 900 950 1000 1050 1100 1150 1200 1250 1.3 1.8 2.3 2.8 3.3 3.8 4.3 4.8 5.3 v bat (v) supply current (na v cc =0v rs1=rs0=1 i batosc2 ( sqwe = 1 ) i batosc 1 ( sqwe = 0 ) i bat vs. temperature v bat = 3.0v 600 650 700 750 800 850 900 950 1000 -40 -20 0 20 40 60 80 temperature (c) supply current (na v cc =0v sqwe=1 sqwe=0 i cc vs. v cc 50 75 100 125 150 175 200 225 250 1.8 2.3 2.8 3.3 3.8 4.3 4.8 5.3 v cc (v) supply current (ua scl=400khz scl=sda =0hz oscillator frequency vs. supply voltage 32768.0 32768.1 32768.2 32768.3 32768.4 32768.5 1.3 1.8 2.3 2.8 3.3 3.8 4.3 4.8 oscillator supply voltage (v) frequency (hz) downloaded from: http:///
ds133 8 7 of 16 pin description pin name function 8 16 1 x1 32.768khz crystal connections. the internal oscillator circuitry is designed for operation with a crystal having a specified load capacitance (c l ) of 12.5pf. an external 32.768khz oscillator can also drive the ds1338. in this configuration, the x1 pin is connected to the external oscillator signal and the x2 pin is left unconnected . note: for more information about crystal selection and crystal layout considerations, refer to application note 58: crystal considerations with dallas real - time clocks . 2 x2 3 14 v bat backup supply input for lithium cell or other energy source. battery voltage must be held between the minimum and maximum limits for proper operation. diodes placed in series between the backup source and the v bat pin may prevent proper operation. if a backup supply is not required, v bat must be grounded. ul recognized to ensure against reverse charging when used with a lithium cell. for more information, visit www.maxim - ic.com/qa/info/ul . 4 15 gnd ground. dc power is provided to the device on these pins. v cc is the primary power input. when voltage is applied within normal limits, the device is fully accessible and data can be written and read. when a backup supply is connected to the device and v cc is below v pf , reads and writes are inhibited. however, the timekeeping function continues unaffected by the lower input voltage. 5 16 sda serial data. input/output pin for the i 2 c serial interface. it is an open drain output and requires an external pullup resistor. the pull up voltage may be up to 5.5v regardless of the voltage on v cc . 6 1 scl serial clock. input pin for the i 2 c serial interface. used to synchronize data moveme nt on the serial interface. the pull up voltage may be up to 5.5v regardless of the voltage on v cc . 7 2 sqw/out square - wave/output driver. when enabled and the sqwe bit set to 1, the sqw/out pin outputs one of four square - wave frequencies (1hz, 4khz, 8kh z, 32khz). it is an open drain output and requires an external pullup resistor. operates with either v cc or v bat applied. the pull up voltage may be up to 5.5v regardless of the voltage on v cc . if not used, this pin may be left unconnected . 8 3 v cc prim ary power supply. when voltage is applied within normal limits, the device is fully accessible and data can be written and read. when a backup supply is connected to the device and v cc is below v pf , reads and writes are inhibited. the backup supply maintains the timekeeping function while v cc is absent. 4C 13 n.c. no connection. these pins are not connected internally, but must be grounded for proper operation. detailed description the ds1338 serial rtc is a low - power, full bcd clock/calendar plus 56 bytes of nv sram. address and data are transferred serially through an i 2 c interface. the clock/calendar provides seconds, minutes, hours, day, date, month, and year information. the end of the month date is automatically adjusted for months with fewer than 31 days, including corrections for leap year. the clock operates in either the 24 - hour or 12 - hour format with am/pm indicator. the ds1338 has a built - in power - sense circuit that detects power failures and automatically switches to the v bat supply. downloaded from: http:///
ds133 8 8 of 16 operation the ds1338 operates as a slave device on the serial bus. access is obtained by implementing a start condition and providing a device identification code, followed by data. subsequent registe rs can be accessed sequentially until a stop condition is execu ted. the device is fully accessible and data can be written and read when v cc is greater than v pf . however, when v cc falls below v pf , the internal clock registers are blocked from any access. if v pf is less than v bat , the device power is switched from v cc to v bat when v cc drops below v pf . if v pf is greater than v bat , the device power is switched from v cc to v bat when v cc drops below v bat . the oscillator and timekeeping functions are maintained from the v bat source until v cc is returned to nominal levels. th e block diagram (figure 3) shows the main elements of the ds1338. an enable bit in the seconds register controls the oscillator. oscillator startup times are highl y dependent upon crystal characteristics, pc board leakage, and layout. high esr and excessive capac itive loads are the major contributors to long start - up times. a circuit using a crystal with the recommended characteristics and proper l ayout usually starts within 1 second. power control the power - control function is provided by a precise, temp erature - compensated voltage reference and a comparator circuit that monitors the v cc level. the device is fully accessible and data can be written and read when v cc is greater than v pf . however, when v cc falls below v pf , the internal clock registers are blocked from any access. if v pf is less than v bat , the device power is switched from v cc to v bat when v cc drops below v pf . if v pf is greater than v bat , the device power is switched from v cc to v bat when v cc drops below v bat . the registers are maintained from the v bat source until v cc is returned to nominal levels ( table 1 ). after v cc returns above v pf , read and write access is allowed after t rec ( figure 1 ). on the first application of power to the device the time and date registers are reset to 01/01/00 01 00:00:00 ( dd/ mm/yy dow hh:mm:ss). the ch bit in the seconds register will be set to a 0. table 1 . power control supply condition read/write access powered by v cc < v pf , v cc < v bat no v bat v cc < v pf , v cc > v bat no v cc v cc > v pf , v cc < v bat yes v cc v cc > v pf , v cc > v bat yes v cc oscillator circuit the ds1338 uses an external 32.768khz crystal. the oscillator circuit does not requir e any external resistors or capacitors to operate. table 2 specifies several crystal parameters for the external crystal. figure 3 shows a functional schematic of the oscillator circuit. the startup time is usually les s than 1 second when using a crystal with the specified characteristics. table 2 . crystal specifications * parameter symbol min typ max units nominal frequency f o 32.768 khz series resistance esr 50 k ? load capacitance c l 12. 5 pf *the crystal, traces, and crystal input pins should be isolated from rf generating signals . refer to application note 58: crystal considerations for dallas real - time clocks for additional specifications. downloaded from: http:///
ds133 8 9 of 16 clock accuracy the accuracy of the clock is dependent upon the accuracy of the crystal and the accur acy of the match between the capacitive load of the oscillator circuit and the capacitive load for which the crystal was trimmed. crystal frequency drift caused by temperature shifts creates additional error. external circuit nois e coupled into the oscillator circuit can result in the clock running fast. figure 4 shows a typical pc board layout for isolating the crystal and oscillator from noise. refer to application note 58: crystal considerations with dallas real - time clocks for detailed information. ds1338c only the ds1338c integrates a standard 32,768hz crystal in the package. typical accuracy at nominal v cc and +25c is approximately 10ppm. refer to application note 58 for information about crystal accuracy vs. temperature. figure 4 . typical pc board layout for crystal rtc and ram address map table 3 shows the address map for the rtc and ram registers. the rtc registers and control regist er are located in address locations 00h to 07h. the ram registers are located in address locations 08h to 3fh. during a multib yte access, when the register pointer reaches 3fh (the end of ram space) it wraps around to location 00h (the beginning of the clock space). on an i 2 c start, stop, or register pointer incrementing to location 00h, the current time and date is transferred to a second set of registers. the time and date in the secondary registers a re read in a multibyte data transfer, while the clock continues to run. this eliminates the need t o re - read the registers in case of an update of the main registers during a read. clock and calendar the time and calendar information is obtained by reading the appropriate register bytes. see figure 6 for the rtc registers. the time and calendar are set or initialized by writing the appropriat e register bytes. the contents of the time and calendar registers are in the bcd format. bit 7 of register 0 is the clock halt (ch) bit. when this bit is set to 1, the oscillator is disabled. when cleared to 0, the oscillator is enabled. the clock can be halted whenever the timekeeping functions are not required, which minimizes v bat current (i batdat ) when vcc is not app lied. the day - of - week register increments at midnight. values that correspond to the day of week are user - defined but must be sequential (i.e., if 1 equals sunday, then 2 equals monday, and so on). illogical time and date ent ries result in undefined opera tion. when reading or writing the time and date registers, secondary (user) buffers are us ed to prevent errors when the internal registers update. when reading the time and date registers, the user buffers are synchronized to the internal registers on any start or stop and when the register pointer rolls over to zero. the countdown chain is reset whenever the seconds register is written. write transfers occur on the acknow ledge from the ds1338. once the local ground plane (layer 2) crystal x1 x2 gnd note: a void routing signals in the crosshatched area (upper left - hand quadrant) of the package unless there is a ground plane between the signal line and the package. downloaded from: http:///
ds133 8 10 of 16 countdown chain is reset, to avoid rollover issues the remaining time and date registers must be written w ithin 1 second. the 1hz square - wave output, if enabled, transitions high 500ms after the seconds data transfer, provided the oscillator is already running. the ds1338 runs in either 12 - hour or 24 - hour mode. bit 6 of the hours register is defined as the 12 - hour or 24 - hour mode - select bit. when high, the 12 - hour mode is selected. in the 12 - hour mode, bit 5 is the am /pm bit, with logic high being pm. in the 24 - hour mode, bit 5 is the 20- hour bit (20 C 23 hou rs). if the 12/ 24 - hour mode select is changed, the hours register must be re - initialized to the new format. on an i 2 c start, the current time is transferred to a second set of registers. the time information is read from these secondary registers, while the clock continues to run. this eliminates the need to re - read the registers in case of an update of the main registers during a read. table 3 . rtc and ram address map address bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 functio n range 00h ch 10 seconds seconds seconds 00 C 59 01h 0 10 minutes minutes minutes 00 C 59 02h 0 12/ 24 am /pm 10 hour hour hours 1C 12 +am/pm 00 C 23 20 hour 03h 0 0 0 0 0 day day 1C7 04h 0 0 10 date date date 01 C 31 05h 0 0 0 10 month month month 01 C 12 06h 10 year year year 00 C 99 07h out 0 osf sqwe 0 0 rs1 rs0 control 08h C 3fh ram 56 x 8 00h C ffh note: bits listed as 0 always read as a 0. downloaded from: http:///
ds133 8 11 of 16 control register (07 h) the control register controls the operation of the sqw/out pin and provides oscillator status. bit # bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 name out 0 osf sqwe 0 0 rs1 rs0 por 1 0 1 1 0 0 1 1 bit 7: output control (out). controls the output level of the sqw/out pin when the square - wave output is disabled. if sqwe = 0, the logic level on the sqw/out pin is 1 if out = 1; it is 0 if out = 0. bit 5: oscillator stop flag (osf). a logic 1 in this bit indicates that the oscillator has stopped or was stopped for some time period and can be used to judge the validity of the clock and calendar data. this bit is edge triggered, and is set to logic 1 when the internal circuitry senses the oscillator has transitioned from a norm al run state to a stop condition. the following are examples of conditions that may cause the osf bit to be set : 1) the first time power is applied. 2) the voltage present on v cc and v bat are insufficient to support oscillation. 3) the ch bit is set to 1, disabling the oscillator. 4) external influences on the crystal (i.e., noise, leakage, etc.). this bit remains at logic 1 until written to logic 0. this bit can only be written to logic 0. a ttempting to write osf to logic 1 leaves the value unchanged. bit 4: square - wave enable (sqwe). when set to logic 1, this bit enables the oscillator output to operate with either v cc or v bat applied. the frequency of the square - wave output depends upon the value of the rs0 and rs1 bits. bits 1 and 0: rate select (rs1 and rs0). these bits control the frequency of the square - wave output when the square - wave output has been enabled. the table below lists the square - wave frequencies that can be selected with the rs bits. square - wave output out rs1 rs0 sqw output sqwe x 0 0 1hz 1 x 0 1 4.096khz 1 x 1 0 8.192khz 1 x 1 1 32.768khz 1 0 x x 0 0 1 x x 1 0 downloaded from: http:///
ds133 8 12 of 16 i 2 c serial data bus the ds1338 supports the i 2 c protocol. a device that sends data onto the bus is defined as a transmitter and a device receiving data is a receiver. the device that controls the message is call ed a master. the devices that are controlled by the master are referred to as slaves. the bus must be controlled by a master device, which gen erates the serial clock (scl), controls the bus access, and generates the start and stop conditions. the ds 1338 operates as a slave on the i 2 c bus. within the bus specifications, a standard mode (100khz maximum clock r ate) and a fast mode (400khz maximum clock rate) are defined. the ds1338 works in both modes. connections to the bus are made through the open - drain i/o lines sda and scl. the following bus protocol has been defined ( figure 5 ). ? data transfer can be initiated only when the bus is not busy. ? during data transfer, the data line must remain stable whenever the clock line is high. changes in the data line while the clock line is high are interpreted as control signals. accordingly, the following bus conditions have been defined: bus not busy: both data and clock lines remain high. start data transfer: a change in the state of the data line, from high to low, while the cloc k is high, defines a start condition. st op data transfer: a change in the state of the data line, from low to high, while the clock line is high, defines the stop condition. data valid: the state of the data line represents valid data when, after a start conditi on, the data line is stable for the duration of the high period of the clock signal. the data on the line must be changed during the low period of the clock signal. there is one clock pulse per bit of data. each data transfer is initiated with a start condition and terminated with a s top condition. the number of data bytes transferred between start and stop conditions is not limited and is determined by the master dev ice. the information is transferred byte - wise and each receiver acknowledges with a ninth bit. acknowledge: each receiving device, when addressed, is obliged to generate an acknowledge after the reception of each byte. the master device must generate an extra clock pulse that is associated with this ackno wledge bit. a device that acknowledges must pull down the sda line during the acknowledge cl ock pulse in such a way that the sda line is stable low during the high period of the acknowledge - related clock pulse. of course, setup and hold times must be taken into account. a master must signal an end of data to the slave by not gene rating an acknowledge bit on the last byte that has been clocked out of the slave. in this case, the slave must leave the data line high to enable the master to generate the stop condition. figure 5 . data transfer on i 2 c serial bus downloaded from: http:///
ds133 8 13 of 16 depending upon the state of the r/ w bit, two types of data transfer are possible: 1) data transfer from a master transmitter to a slave receiver. the master transmits the first byte (the slave address). next follows a number of data bytes. the slave returns an acknowledge bit after each received byte. data is transferred with the most significant bit (msb) first. 2) data transfer from a slave transmitter to a master receiver. the master transmits the first byte (the slave address). the slave then returns an acknowledge bit, which is followed by t he slave transmitting a number of data bytes. the master returns an acknowledge bit after all received bytes other than the last byte. at the end of the last received byte, a not acknowledge is returned. the master device ge nerates all of the serial clock pulses and the start and stop conditions. a transfer is ended with a stop condition or with a repeated start condition. since a repeated start condition is also the beginning of the next serial transfer , the b us is not released. data is transferred with the most significant bit (msb) first. the ds1338 can operate in the following two modes: 1) slave receiver mode (write mode): serial data and clock are received through sda and scl. an acknowledge bit is transmitted after each byte is received. start and stop conditions ar e recognized as the beginning and end of a serial transfer. hardware performs address recognition after reception of the slave address and direction bit ( figure 6 ). the slave address byte is the first byte received after the master generates the start condition. the slave address byte contains the 7 - bit ds1338 address 1101000 followed by the direction bit (r/ w ), which, for a write, is 0. after receiving and decoding the slave address byte, the slave outputs an acknowledge on the sda line. after the ds1338 acknowledges the slave address and write bit, the master transmits a register address to the ds1338. this sets the register pointer on the ds1338, with ds1338 acknowledging the transfer. the master may then transmit zero or more bytes of data, with the ds1338 acknowledging each byte received. the register pointer increments after each data byte is transf erred. the master generates a stop condition to terminate the data wri te. 2) slave transmitter mode (read mode): the first byte is received and handled as in the slave receiver mode. however, in this mode, the direction bit indicates that the transfer directi on is reversed. the ds1338 transmits serial data on sda while the serial clock is input on scl. start and sto p conditions are recognized as the beginning and end of a serial transfer ( figure 7 ). the slave address byte is the first byte received after the master generates the start condition. the slave address byte contains the 7 - bit ds1338 address 1101000 followed by the direction bit (r/ w ), which, for a read, is 1. after receiving and decoding the slave address byte, the slave outputs an acknowledge on the sda line. the ds1338 then starts transmitting data using the register address pointed to by the register pointer. if the register pointer is not set before the initiat ion of a read mode, the first address that is read is the last one stored in the register pointer. the register pointer is incremen ted after each byte is transferred. the ds1338 must receive a not acknowledge to end a read. downloaded from: http:///
ds133 8 14 of 16 figure 6 . data write slave receiver mode figure 7 . data read (from current pointer location) slave t ransmitter mode figure 8 . data read (write pointer, then read slave receive and transmit ... a xxxxxxxx a 1101000 s 1 xxxxxxxx a xxxxxxxx xxxxxxx x a p a s - start a - acknowledge (ack) p - stop a - not acknowledge (nack) data transferred (x+1 bytes + acknowledge) note: last data byte is followed by a nack master to slave slave to master ... a xxxxxxxx xxxxxxxx a xxxxxxxx a xxxxxxxx a p s - start sr - repeated start a - acknowledge (ack) p - stop a - not acknowledge (nack) data transferred (x+1 bytes + acknowledge ) note: last data byte is followed by a nack a xxxxxxxx a 1101000 s 0 a 1101000 sr 1 master to slave slave to master ... a xxxxxxxx a s 0 xxxxxxxx a xxxxxxxx a xxxxxxxx a p s - start a - acknowledge (ack) p - stop data transferred (x+1 bytes + acknowledge) 1101000 master to slave slave to master downloaded from: http:///
ds133 8 15 of 16 handling, pcb layout , and assembly the ds1338c package contains a quartz tuning - fork crystal. pick - and - place equipment may be used, but precautions should be taken to ensure that excessive shocks are avoided. ultrasonic cleaning should be avoided to prevent damage to the crystal. exposure to reflow is limited to 2 times maximum. avoid running signal traces under the package, unless a ground plane is placed between the package and the signal line. all n.c. (no connect) pins must be connected to ground. the rohs and lead - free/rohs packages may be reflowed using a reflow profile that complies with jedec j - std - 020. moistu re - sensitive packages are shipped from the factory dry - packed. handling instructions listed on the package label must be followed to prevent damage during reflow. refer to the ipc/jedec j - std - 020 standard for moisture - sensitive device (msd) classifications . pin configurations chip information transistor count: 12,231 process: cmos thermal information part theta -j a (c/w) theta -j c (c/w) 8 so 132 38 8 sop 206.3 42 16 so 73 23 package information for the latest package outline information and land patterns (footprints) , go to www.maxim - ic.com/packages . note that a +, #, or - in the package code indicates rohs status only. package drawings may show a different suffix character, but the drawing pertains to the package regardless of rohs status. package type package code outline no. land pattern no. 8 so s8+4 21 - 0041 90 - 0096 8 max u8+1 21 - 0036 90 - 0092 16 so w16#h2 21 - 0042 90 - 0107 so, sop sqw/out 1 2 3 4 8 7 6 5 x1 x2 v bat gnd v cc scl sda top view scl sda gnd v bat sqw/out v cc n.c. n.c. n.c. n.c. n.c. n.c. n.c. n.c. n.c. n.c. ds1338c so (300 mils) top view ds1338 downloaded from: http:///
16 of 16 maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a maxim product. no circuit patent licenses are implied. maxim reserves the right to change the circuitry and specifications without notice at a ny time. maxim integrated products, 1 6 0 rio robles , san jose , ca 9 5134 408 - 601 - 100 0 ? 201 5 maxim integrated products maxim is a registered trademark of maxim integrated products, inc. revision history revision date description pages chang ed 100108 modified the features bullet to indicate that battery - backed ram has unlimited writes. 1 removed leaded part numbers from the ordering information table. 1 removed the pullup resistor voltage spec from the recommended dc operating conditions table and added it to the pin descriptions. 2, 7 updated the block diagram (figure 3) to show that sqw is open drain. 5 added the initial por state for time and date registers in the power control section. 8 added text to explain the use of the oscillator bit to control battery current in the clock and calendar section. 9 9/11 updated the absolute maximum ratings , recommended dc operating conditions , dc electrical characteristics , power control , oscillator circuit , table 3, handling, pbb layout, and assembly , thermal information , and package information . 2, 8, 10, 15 3/12 corrected the ch bit por condition from 1 to 0 in the power control section 8 4/15 revised benefits and features section 1 downloaded from: http:///

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